CMOS Memory sense amplifier

ABSTRACT

A complementary metal oxide semiconductor (CMOS) field effect transistor (FET) memory sense amplifier to detect a relatively small differential voltage that is superimposed on a relatively large common mode precharge signal. The sense amplifier is implemented so as to provide latched output signals after a short time delay and in response to sensed input signals that are supplied via a pair of data bus lines.

The invention herein described was made in the course of or under acontract or subcontract with the U.S. Air Force.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a radiation hardened, CMOS memory senseamplifier that is sensitive to relatively small differential voltagesignals supplied thereto from a selected memory cell via a pair of databus lines.

2. Statement of the Prior Art

As is known to those skilled in the art, many sense amplifiers areavailable to detect output signals derived from an array ofsemiconductor memory cells. However, these prior art memory senseamplifiers are typically characterized by relatively low inputimpedance. As a result, the loading effects of the prior art senseamplifiers may cause the undesirable destruction or alteration of datathat is stored in a selected memory cell when that memory cell is reador sensed. Otherwise, a time consuming refresh cycle is required tore-establish the contents of the selected memory cell after the readoperation is completed. Moreover, low input impedance renders the priorart sense amplifiers undesirably susceptible to internal disturbancesthat may be caused as the result of a nuclear radiation event.

Examples of prior art sense amplifiers that include some of theshortcomings described by the foregoing paragraph are found in thefollowing U.S. patents:

U.S. Pat No. 3,959,781 May 25, 1976

U.S. Pat. No. 3,978,459 Aug. 31, 1976

U.S. Pat. No. 4,010,453 Mar. 1, 1977

U.S. Pat. No. 4,028,557 June 7, 1977

U.S. Pat. No. 4,031,415 June 21, 1977

SUMMARY OF THE INVENTION

Briefly, and in general terms, a CMOSFET memory sense amplifier isdisclosed that is sensitive to relatively small differential voltageinput signals supplied by a pair of data bus lines. The sense amplifieris comprised of a data latch and a pair of inverters, each inverterrespectively connected between an output terminal of the data latch andan output terminal of the sense amplifier. The operation of the senseamplifier is controlled by recurring strobe signals. Each one of thepair of data bus input lines is respectively connected between an arrayof memory cells and the gate electrode of a field effect transistor thatforms the data latch. Therefore, the present sense amplifier ischaracterized by a high input impedance. Moreover, the present senseamplifier is adapted to drive a non-symmetrical (capacitive) load fromthe output terminals thereof.

In operation, the sense amplifier is initially rendered in a quiescentmode, prior to the sense operation, during which time the pair of databus lines are precharged to a common mode voltage level. In a subsequenttime interval, the sense amplifier is rendered in an active mode bymeans of the strobe signals, during which time the contents of aselected memory cell are sensed via the pair of data bus lines. Thesensed memory cell information is stored at the output terminals of thedata latch, whereby the logical state of the sense amplifier ispreserved during the following quiescent time interval when the inputmemory cell information signals are terminated and the data bus linesare again precharged to the common mode voltage level.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram representative of a typical interconnection ofan array of conventional semiconductor memory cells with a plurality ofthe sense amplifiers of the present invention.

FIG. 2 is a schematic circuit to show a preferred implementation of theCMOS sense amplifier which forms the present invention.

FIG. 3 shows the sequence of the signal waveforms occurring during asense cycle and appearing on a pair of the data bus lines and at theoutput terminals of the presently disclosed sense amplifier.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 shows a typical interconnection of an array of conventionalsemiconductor memory cells with a plurality of identical senseamplifiers 10, which sense amplifiers 10 form the present invention.Inasmuch as the interconnection of the memory cell array with the senseamplifiers 10 is well known, only a brief description thereof ispresented herein. The output terminals of each of a column of the memorycells are connected to a respective pair of BIT and BIT data bus lines.Each pair of BIT and BIT data bus lines is connected to input terminalsof a respective sense amplifier 10 so as to provide differential signalsthereto that are indicative of the logical state of a selected memorycell from each column of memory cells. Each memory cell from a row ofthe memory cells is connected to a respective row select line. A rowselect line applies an enabling signal to selectively energize aparticular memory cell for the purpose of reading or writing logicalinformation via the corresponding pair of data bus lines. A suitablesource of strobe input signals is connected, via a common strobe signalline, to each of the sense amplifiers 10 to, thereby, sychronouslycontrol the operation thereof.

In accordance with the instant invention and referring to FIG. 2 of thedrawings, a preferred CMOS sense amplifier configuration is illustrated.The sense amplifier 10 includes first and second n-channel field effecttransistors (FETs) Q₁ and Q₂. FET Q₁ is connected between an electricaljunction 12 and an electrical junction 14. FET Q₂ is connected betweenthe electrical junction 12 and an electrical junction 16. A first BITdata bus line is connected to an input terminal of the sense amplifier10 at the gate electrode of the n-channel FET Q₁. The opposite state BITdata bus line is connected to another input terminal of the senseamplifier 10 at the gate electrode of the n-channel FET Q₂. By virtue ofthe connections of the BIT and BIT data bus lines to the gate electrodesof FETs Q₁ and Q₂, respectively, the loading of the data bus lines is,thereby, reduced to the input capacitances of FETs Q₁ and Q₂. As aresult of these input connections, and unlike the prior art senseamplifiers, a high input impedance is achieved. Therefore, the loadpresented to a pair of data bus lines by the sense amplifier 10 isminimized, so as to prevent destruction of data that is stored in aselected memory cell and to reduce the deterioration of the informationsignals that are detected by the sense amplifier during a senseoperation.

A first p-channel FET Q₃ is connected between the electrical junction 14and an electrical junction 18. A second p-channel FET Q₄ is connectedbetween the electrical junctions 16 and 18. The electrical junction 18is connected to a source of relatively positive supply voltage,designated V_(DD), which is typically +11 volts d.c. FETs Q₃ and Q₄ arecross-connected relative to one another. That is, the gate electrode ofFET Q₃ is connected to one conduction path electrode of FET Q₄ at theelectrical junction 16. The gate electrode of FET Q₄ is connected to oneconduction path electrode of FET Q₃ at the electrical junction 14. Therespective conduction paths of FETs Q₁ and Q₃ and FETs Q₂ and Q₄ areconnected in electrical series between the electrical junctions 12 and18. Therefore, the interconnection of FETs Q₁ -Q₄ forms a data latch 19which, as will be explained in greater detail hereinafter, maintains itslogical state subsequent to the termination of the sense amplifier inputsignals that are supplied via the BIT and BIT data bus lines.

The output terminals (i.e. electrical junctions 14 and 16) of the datalatch 19 are respectively connected to a pair of inverters 20 and 22.Inverter 20 is comprised of a p-channel FET Q₇ and an n-channel FET Q₈.The conduction paths of FETs Q₇ and Q₈ are connected together inelectrical series between the electrical junctions 12 and 18. The gateelectrodes of FETs Q₇ and Q₈ are connected together at the data latchoutput terminal 14. A first output terminal, designated OUT, of thesense amplifier 10 is connected at a convenient point between the seriesconnected conduction paths of FETs Q₇ and Q₈. Inverter 22 is comprisedof a p-channel FET Q₉ and an n-channel FET Q₁₀. The conduction paths ofFETs Q₉ and Q₁₀ are connected together in electrical series between theelectrical junctions 12 and 18. The gate electrodes of FETs Q₉ and Q₁₀are connected together at the data latch output terminal 16. A secondoutput terminal, designated OUT, of the sense amplifier 10 is connectedat a convenient point between the series connected conduction paths ofFETs Q₉ and Q₁₀. Inverters 20 and 22 buffer the data latch and providethe required output to drive a load (not shown). By way of example, theinverters 20 and 22 are adapted to drive a relatively large,non-symmetrical load capacitance.

Two additional FETs Q₅ and Q₆ are employed to either selectively enableor disable the sense amplifier 10 in response to an external strobesignal. A p-channel FET Q₅ is connected between the data latch outputterminals, which comprise the electrical junctions 14 and 16. Ann-channel FET Q₆ is connected between the electrical junction 12 and asource of relatively negative supply voltage, such as ground. The gateelectrodes of FETs Q₅ and Q₆ are connected together at an electricaljunction 24 to receive a supply of strobe signals. The strobe signalscontrol the conductivity of FETs Q₅ and Q₆ and, as will also beexplained in greater detail hereinafter, synchronously control theoperation of the sense amplifier 10. Moreover, FETs Q₅ and Q₆ act tobias the data latch to a quiescent state in preparation for aninformation sensing operation.

In a preferred embodiment of the invention, the channel lengths of FETsQ₁ -Q₁₀ are approximately identical. However, FET Q₆ (which provides theground return for the sense amplifier 10) is selected with asubstantially larger channel width than those of FETs Q₇ and Q₉.Moreover, the channel widths of FETs Q₇ and Q₉ are larger than those ofFETs Q₃, Q₄, Q₅, Q₈ and Q₁₀. What is more, the channel widths of FETsQ₃, Q₄, Q₅, Q₈ and Q₁₀ are larger than those of the data latch FETs Q₁and Q₂. By way of example, the channel widths of FET Q₆ is approximatelyfive times larger than those of FETs Q₁ and Q₂ and two and one halftimes larger than those of FETs Q₃, Q₄, Q₅, Q₈ and Q₁₀. The channelwidths of FETs Q₇ and Q₉ are approximately three times larger than thoseof FETs Q₁ and Q₂.

A typical sequence of the signal wave forms appearing on a pair of BITand BIT data bus lines and at the output terminals OUT and OUT during asense cycle of the presently disclosed sense amplifier 10 of FIG. 2 isillustrated in FIG. 3. The operation of the sense amplifier 10 isdisclosed while referring concurrently to FIGS. 2 and 3 of the drawings.During a first interval of time, designated t₁, that occurs prior to thesensing of an information signal from a selected memory cell, each oneof the BIT and BIT data bus lines is precharged to a relatively positivecommon mode voltage level, such as V_(DD). During the t₁ precharge timeinterval, the strobe signal that is applied to the sense amplifier andto the respective gate electrodes of FETs Q₅ and Q₆ at the electricaljunction 24 has a relatively low (e.g. ground) signal level. Hence, FETQ₆ is rendered non-conductive which, thereby, separates the senseamplifier 10 from the relatively negative source of supply potential(i.e. ground) and, accordingly, disables the sense amplifier. As aresult, the sense amplifier 10 operates in a quiescent state. The outputterminals (i.e. electrical junctions 14 and 16) of the sense amplifierdata latch 19 receive voltages equivalent to +V_(DD) -V_(TP), whereV_(TP) represents the threshold voltage drop of a correspondingp-channel FET Q₃ or Q.sub. 4. During the t₁ time interval, p-channel FETQ₅ is rendered conductive, inasmuch as sufficient threshold voltage isapplied to the gate-to-source junction thereof. Thus, the electricaljunctions 14 and 16 are connected together via the conduction path ofFET Q₅ so that the voltage applied to each of the electrical junctions14 and 16 is identical. The voltage that is applied to the outputterminals 14 and 16 of the data latch 19 is approximately one-half therelatively positive source voltage V_(DD). Therefore, each of the FETsQ₇ -Q₁₀, which forms the inverters 20 and 22, would be undesirablybiased in the Class A region if the inverters 20 and 22 were otherwisereferenced to ground via the conduction path of FET Q₆. However,inasmuch as FET Q₆ is rendered non-conductive, the ground return ofinverters 20 and 22 is removed. Therefore, relatively high biascurrents, that could be undesirably conducted through each of theinverter FETs Q₇ -Q₁₀, are avoided.

The sensing operation begins during an interval of time designated t₂,when the common mode voltage V_(DD) of one of the BIT or BIT data buslines is discharged towards ground. A particular memory cell (e.g., thatdesignated cell A in FIG. 3) is accessed by means of a row select line(as disclosed when referring to FIG. 1). Output information signals thatare stored in the selected memory cell typically appear on the BIT andBIT data bus lines after a relatively long response time, due to thecapacitance presented by the data bus lines. In order to minimize thedata access time during the sense interval of time, t₂, it is,therefore, desirable for the sense amplifier 10 to be responsive to arelatively small voltage differential occurring between the data buslines.

By the end of the t₂ time interval, one of the data bus lines (e.g. theBIT data line) is discharged by a voltage ΔV. Moreover, the strobesignal that is applied to the gate electrodes of FETs Q₅ and Q₆ at theelectrical junction 24 switches from ground to a relatively high signallevel (e.g. V_(DD)). FET Q₆ is, thereby, rendered conductive, and arelatively negative supply voltage (i.e. ground) is applied via theconduction path thereof to each of the FETs Q₁ -Q₄ which form the datalatch 19 and to the FETs Q₇ -Q₁₀ which form inverters 20 and 22. Thesense amplifier 10 is, thereby, rendered in an active state. Also, bythe end of the t₂ time interval, FET Q₅ is rendered non-conductive,inasmuch as insufficient threshold voltage is applied to thegate-to-source junction thereof, and electrical junctions 14 and 16 may,thereby, assume different voltage levels. Therefore, the n-channel FETsQ₁ and Q₂ present a load impedance to the p-channel FETs Q₃ and Q₄. Theactual load impedance is dependent upon the voltage level of the memorycell information signals that are applied to the input terminals of thesense amplifier 10 via the pair of BIT and BIT data bus lines. By way ofexample, if the information voltage level on the BIT data bus linedischarges from V_(DD) towards ground by a voltage ΔV, FET Q₂ provides alower impedance at the end of the t₂ time interval than that provided byFET Q₁. Hence, electrical junction 16 charges to a lower voltage thanthat of electrical junction 14. The resulting differential voltage thatoccurs between the output terminals (i.e. electrical junctions 14 and16) of the data latch 19 is regenerative due to the previously disclosedcross-coupled interconnection of FETs Q₃ and Q₄. The regenerative natureof the differential voltage that is applied to the electrical junctions14 and 16 ultimately causes electrical junction 16 to fully discharge toa relatively negative voltage level (approximately ground) andelectrical junction 14 to fully charge to a relatively positive voltagelevel (approximately V_(DD)) to thereby cause the sense amplifier datalatch 19 to latch.

The aforementioned regenerative action of the differential voltage atthe data latch output terminals 14 and 16 minimizes the response time,t_(d), of the sense amplifier 10 at the beginning of the next intervalof time, designated t₃. During the balance of the t₃ time interval,wherein the strobe signal continues to have a relatively high signallevel, the sense amplifier 10 stores information signals at the outputterminals 14 and 16 of the data latch 19 in response to input signalssupplied by the BIT and BIT data bus lines. Once the sense amplifier 10assumes a given output state (i.e. after completion of the response timet_(d)), the sense amplifier maintains its output state for the remainderof the t₃ time interval. At the beginning of the following interval oftime, designated t₄, during which time interval the strobe signal alsomaintains a high signal level, the input signals supplied to the senseamplifier via the BIT and BIT data bus lines are terminated, and thedata bus lines are returned to the positive common mode prechargevoltage level. Nevertheless, the output state of the sense amplifier 10is preserved throughout the t₄ time interval after the termination ofthe sensed input signals.

During the successive t₃ and t₄ time intervals, inverters 20 and 22sense the voltages at the output terminals 14 and 16, respectively, ofthe sense amplifier data latch 19. The inverters 20 and 22 providesufficient gain to drive the output (capacitive) load from the senseamplifier output terminals OUT and OUT. Since the inverter 20 has anidentical implementation to that of the inverter 22, electricaljunctions 14 and 16 are provided with equal load capacitance regardlessof any eventual imbalance caused by nonsymmetrical output loading. Thevoltage signals at electrical junctions 14 and 16 are, therefore,unaffected by an unbalanced load during the critical time (at the end oft₂) when the strobe signal that is applied to the electrical junction 24has a positive going transistion level. Hence, during the t₃ and t₄ timeintervals, the data that is stored by the sense amplifier 10 is valid.That is, the information signals stored by the sense amplifier 10 are ina condition that is suitable for application of external utilizationmeans (not shown) via the sense amplifier output terminals OUT and OUT.Moreover, the t.sub. 4 time interval is utilized to prepare the memorycell array for the selection of the next memory cell (e.g., thatdesignated cell B in FIG. 3) from the array thereof while the outputdata of the previously selected memory cell (cell A) continues to beheld and sampled.

During the subsequent t₁ precharge time interval of the next sensecycle, the strobe signal is again terminated (i.e. assumes a relativelylow signal level), and the sense amplifier output data is no longervalid. When the strobe signal returns to the relatively low signallevel, the sense amplifier accordingly returns to its quiescent state.Moreover, as previously disclosed, FET Q₆ is rendered non-conductive toseparate the sense amplifier 10 from the source of relatively negativesupply voltage (ground). Hence, FET Q₅ is once again renderedconductive. The voltage differential that previously existed during thepreceding sense cycle between electrical junctions 14 and 16 is,thereby, discharged via the conduction path of FET Q₅ in preparation forthe next sense operation.

It will be apparent that while a preferred embodiment of the inventionhas been shown and described, various modifications and changes may bemade without departing from the true spirit and scope of the invention.For example, each of the FETs Q₁ -Q₁₀ which form the present senseamplifier 10 may be fabricated from a layer of silicon on a sapphiresubstrate. By virtue of the silicon on sapphire (SOS) fabricationtechniques and the relatively high input impedance provided to the BITand BIT data bus lines, the susceptibility of the memory cell array tointernal disturbances of the instant sense amplifier 10 that may becaused by the undesirable effects of a nuclear radiation event issubstantially reduced. Thus, the information signals that are stored inthe memory cell array are protected from loss or alteration as aconsequence of a nuclear radiation occurrence.

Having thus set forth a preferred embodiment of the instant invention,what is claimed is:
 1. A sense amplifier connected to an array of memorycells by means of a pair of data bus lines so as to sense informationsignals contained in selected ones of the memory cells, said senseamplifier comprising:first and second pairs of multi-terminal transistordevices having respective conduction paths and control electrodes, firsttransistor devices from each of said first and second pairs thereofconnected in electrical series with one another between first and secondelectrical junctions, second transistor devices from each of said firstand second pairs thereof connected in electrical series with one anotherbetween third and fourth electrical junctions, the control electrode ofthe first transistor device of said first pair thereof connected to aconduction path electrode of the second transistor device of said firstpair thereof, and the control electrode of the second transistor deviceof said first pair thereof connected to a conduction path electrode ofsaid first transistor device of said first pair thereof, each of therespective control electrodes of the transistor devices of said secondpair thereof connected to a corresponding data bus line, whereby arelatively high input impedance is achieved for said sense amplifier,each of the multi-terminal transistor devices of the first pair thereofbeing a p-channel field effect transistor, each of the multi-terminaltransistor devices of the second pair thereof being a n-channel fieldeffect transistor, said first and third electrical junctions beingcommon electrical junctions, said second and fourth electrical junctionsbeing common electrical junctions, a source of recurring strobe inputsignals to control the conductivity of said sense amplifier, a firstsource of supply voltage, a first additional multi-terminal transistordevice having a conduction path and a control electrode, the controlelectrode of said first additional transistor device connected to saidsource of strobe signals, and the conduction path of said firstadditional transistor device selectively connecting each of the secondand fourth electrical junctions to said first source of supply voltageto thereby enable said sense amplifier, a second source of supplyvoltage wherein the first and third electrical junctions are connectedto said second source of supply voltage, a second additionalmulti-terminal transistor device having a conduction path and a controlelectrode, the control electrode of said second additional transistordevice connected to said source of strobe signals, and the conductionpath of said second additional transistor device connected between theconnection of the control electrode of the first transistor device ofsaid first pair thereof to the conduction path electrode of the secondtransistor device of said first pair thereof and the connection of thecontrol electrode of the second transistor device of said first pairthereof to the conduction path electrode of the first transistor deviceof said first pair thereof, said first and second additionalmulti-terminal transistor devices being field effect transistors havingan opposite conductivity type relative to one another, theinterconnection of said first and second pairs of multi-terminaltransistor devices forms a data latch, the control electrodes of each ofsaid second pair of transistor devices corresponding to data latch inputterminals, the connection of the control electrode of the firsttransistor device of said first pair thereof to the conduction pathelectrode of the second transistor device of said first pair thereof andthe connection of the control electrode of the second transistor deviceof said first pair thereof to the conduction path electrode of the firsttransistor device of said first pair thereof corresponding to data latchoutput terminals, first and second amplifier stages, each of said stageshaving input and output terminals, the data latch output terminalsrespectively connected to the input terminals of said first and secondamplifier stages, each of said first and second amplifier stages beingcomprised of a pair of series connected field effect transistors havingan opposite conductivity type relative to one another, and said data buslines being precharged to reduce amplifier access time to data stored insaid cells and to preserve said data in a radiation environment.
 2. Asense amplifier to interface with an array of memory cells via a pair ofdata bus lines, said sense amplifier comprising:a source of supplyvoltage, a data latch having first and second input and output terminalsand comprising first, second, third and fourth transistor devices, eachhaving a respective control electrode and a conduction path, said firstand second transistor devices connected in electrical series with oneanother and said third and fourth transistor devices connected inelectrical series with one another, the control electrodes of saidsecond and fourth transistor devices corresponding to the first andsecond data latch input terminals to be respectively connected to thepair of data bus lines to provide a high sense amplifier inputimpedance, a fifth transistor device having a control electrode and aconduction path that is connected between the first data latch outputterminal including an interconnection of the control electrode of saidfirst transistor device with a conduction path electrode of said thirdtransistor device, and the second data latch output terminal includingan interconnection of the control electrode of said third transistordevice with a conduction path electrode of said first transistor device,a sixth transistor device having a control electrode and a conductionpath that is connected between said source of supply voltage and anelectrical junction including conduction path electrodes of said secondand fourth transistor devices, a source of supply of recurring strobesignals connected to the respective control electrodes of said fifth andsixth transistor devices, whereby said fifth transistor device isrendered conductive during a first strobe interval in order to equalizethe signals applied to the data latch output terminals and to disableand sense amplifier, and said sixth transistor device is renderedconductive during a second strobe interval to enable said senseamplifier to read information from a selected one of the array of memorycells via said data bus lines and to store an indication of theinformation at the data latch output terminals, said data bus linesbeing precharged, and the channel widths of the first and thirdtransistor devices being larger than the channel widths of said secondand fourth transistor devices, whereby any data appearing at said outputterminals will be preserved during precharging of said data bus lines.3. The sense amplifier recited in claim 2, further including first andsecond amplifier stages,the first and second data latch output terminalsrespectively connected to input terminals of said first and secondamplifier stages.
 4. The sense amplifier recited in claim 2, whereinsaid first, third and fifth transistor devices are p-channel fieldeffect transistors, andsaid second, fourth and sixth transistor devicesare n-channel field effect transistors.
 5. The sense amplifier recitedin claim 4, wherein the channel width of the sixth field effecttransistor is substantially larger than those of the first, second,third, fourth and fifth field effect transistors.